1. Field of Invention
The present invention relates to a method of manufacturing integrated circuits. More particularly the present invention relates to a method of manufacturing the capacitor of a dynamic random access memory (DRAM).
2. Description of Related Art
DRAM is a type of high-density integrated circuit on a silicon chip widely used in the electronic industry for storing digital information. Digital information is stored in the capacitor of a memory unit. Normally, the value stored within a memory cell depends on the amount of electric charges a capacitor is holding at a particular moment. Each memory unit has a particular set of peripheral circuits that serve to store and retrieve data.
After years of development, a memory unit now comprises a transfer field effect transistor (TFET) and a storage capacitor, only. FIG. 1 is a circuit diagram showing a single memory unit of a DRAM device. As shown in FIG. 1, the charged or discharged state of a capacitor C can be used for storing digital data. The most common memory configuration is to store a single bit of data in each capacitor C. When the capacitor C is fully discharged, a logic value of "0" is held. On the other hand, when the capacitor C is fully charged, the logic value of "1" is held.
There is a dielectric layer 102 between the upper electrode 101 and the lower electrode 100 of the capacitor C. The dielectric layer 102 provides a dielectric constant between the electrodes 100 and 101. The lower electrode 100 of the capacitor C is connected to a bit line through a transfer field effect transistor T so that charging and discharging of the capacitor can be carried out. In fact, the source terminal of the transistor T is connected to the bit line BL while the drain terminal is connected to the lower electrode 100. In addition, the gate terminal is connected to a word line WL so that connection between the bit line BL and the capacitor can be selected through controlling the signal sent to the word line WL.
As the number of transistor devices within a given chip increases, dimensions of each transistor must shrink and the transistors must be closer to each other. Therefore, when a capacitor is charged, keeping the signal-to-noise ratio below a certain threshold may be difficult. On the other hand, if the amount of charges stored in each capacitor is reduced to counteract noise generation, capacitor refresh frequency may increase.
Since the area occupied by a capacitor is restricted by the size of each memory cell, the only means to increase the capacitance of a capacitor is to utilize the third dimension. In other words, three-dimensional capacitors must be used. The most common types of three-dimensional capacitor structures include the trench type, the cylindrical type and the stack type. Because the trench type is more difficult to fabricate, it is rarely used nowadays. The cylindrical type and the stack type of capacitor extend vertically upwards. Since both the cylindrical and stack type of capacitor are capable of considerably increasing the capacitance and are easier to produce, they are used more frequently.
FIGS. 2A through 2G are schematic, cross-sectional views showing the progression of steps in a manufacturing process for producing a conventional cylindrical capacitor in DRAM.
First, as shown in FIG. 2A, a silicon substrate 200 having a MOS transistor (not shown) thereon is provided. Then, an oxide layer 202 and a silicon nitride layer 204 are sequentially formed over the substrate 200. The silicon nitride layer 204 serves as a barrier layer in subsequent etching operation.
Next, as shown in FIG. 2B, photolithographic and etching processes are carried out to pattern the silicon nitride layer 204 and the oxide layer 202 to form a contact window opening 206. The contact window opening 206 exposes a portion of the substrate 200, for example, a doped region of the MOS device. Thereafter, a polysilicon layer 208 is deposited over the silicon nitride layer 204 such that the contact window opening 206 is completely filled.
Next, as shown in FIG. 2C, the polysilicon layer 208 is etched back to form a polysilicon layer 208a whose top surface is level with the silicon nitride layer 204.
In the subsequent step, as shown in FIG. 2D, an oxide layer 210 is formed over the silicon substrate 200, and then photolithographic and etching processes are again carried out to pattern the oxide layer 210 to form an opening 212. The opening 212 exposes a portion of the polysilicon layer 208a and the silicon nitride layer 204. Then, another polysilicon layer 214 is formed over the substrate 200. The polysilicon layer 214 covers the opening 212 and the oxide layer 210 so that the polysilicon layer 214 and the polysilicon layer 208a are in contact with each other. Thereafter, an oxide layer 216 is formed over the polysilicon layer 214.
Next, as shown in FIG. 2E, the oxide layer 216 is etched back using the polysilicon layer 214 as an etching end point After that, the polysilicon layer 214 is also etched back using the oxide layer 210 as another etching end point. Ultimately, a polysilicon layer 214a and an oxide layer 216a are retained within the opening 212.
Next, as shown in FIG. 2F, a wet etching operation is carried out to remove the remaining oxide layer 216a and oxide layer 210 using the silicon nitride layer 204 as an etching barrier layer.
Thereafter, as shown in FIG. 2G, an insulation layer 218 is formed over the substrate 200. The insulation layer 218, for example, can be an oxide/nitride/oxide (ONO) composite layer. Finally, a polysilicon layer 220 is deposited over the insulation layer 218 to form a complete cylindrical DRAM capacitor.
However, the aforementioned method of fabricating cylindrical capacitor requires several photolithographic and etching operations with different masks. Since the dimensions of devices are reduced with each newer generation of silicon chip, making node contacts that align correctly with the intended source/drain region on a substrate will be very difficult.
In light of the foregoing, there is a need to provide an improved method of fabricating cylindrical DRAM capacitor.